1. Field of the Invention
The present invention relates to a time-to-digital converter, and more particularly, to a sub-exponent time-to-digital converter using a phase-difference enhancement device.
2. Description of the Related Art
In general, a time-to-digital converter is used in almost all digitally-controlled phase-locked loops (PLLs). In addition, the time-to-digital converter also used as a means for measuring a very short time interval, and is utilized in very various fields. However, the time-to-digital converter is required to have a high resolution in order to minimize a quantization error.
FIG. 1 is a circuit diagram of a conventional time-to-digital converter.
Referring to FIG. 1, the conventional time-to-digital converter 100 includes a delay signal generation section 110 and a digital signal generation section 120.
The delay signal generation section 110 is constituted with a plurality of delay elements D1 to D3, which are coupled in series with each other and are configured to gradually delay the phase of a first input signal and to generate a plurality of phase-delayed signals delay1 to delay3. The delay elements generally are constructed with inverters capable of implementing a shortest delay time in a semiconductor process.
The digital signal generation section 120 is constituted with a plurality of D flip-flops D-FF1 to D-FF3, which latches the phase-delayed signals delay1 to delay3 to generate a plurality of output signal Q1 to Q3 in response to a second input signal.
In this case, when it is assumed that the time-to-digital converter receives first and second input signals having a reference phase difference Δt between the input signals, and all the delay elements cause the same delay time τ, the conventional time-to-digital converter operates as follows.
The delay signal generation section 110 receives the first input signal, and generates a plurality of delay signals delay1 to delay3 having mutually different delay times through the plurality of delay elements. In this case, as the first input signal passes through the delay elements one after another, the first input signal is delayed longer and longer.
The digital signal generation section 120 receives the plurality of delay signals, and generates digital signals corresponding to the phase difference Δt. That is, the D flip-flops D-FF1 to D-FF3 of the digital signal generation section 120 latch the delay signals to generate output signals Q1 to Q3, respectively, in response to the second input signal, wherein, if the first input signal is delayed greater than the reference phase difference Δt, a corresponding D flip-flop generates an output signal of “0,” and if not, a corresponding D flip-flop generates an output signal of “1.”
Therefore, through the examination of the outputs of the D flip-flops, it is possible to find the phase difference between the first and second input signals. That is, when N number of D flip-flops generate an output signal of “1,” the phase difference between the first and second input signals is calculated by “N*τ.”
In this case, τ designates a minimum delay time into which the time-to-digital converter can resolve a time. That is, when the phase difference between two input signals is equal to or less than τ, it is impossible to perform conversion into a corresponding digital signal. In this case, there is a disadvantage in that τ is determined according to semiconductor processes. As described above, the conventional time-to-digital converter has a limitation in the minimum delay time which can be obtained in a semiconductor process, and requires high power consumption and a wide area on a semiconductor chip due to a large number of D flip-flop and serially-coupled delay elements.